SUMMARY OF THE INVENTION
A circuit package comprises at least one integrated circuit chip mounted in a depression or hole formed in a semiconductor wafer such that there is relatively little free space between the chip and the wall forming the hole. The surface of the chip lies essentially in the same plane as the surface of the wafer. Circuit means, including bonding pads are associated with said wafer and said chip, said bonding pads being used to interconnect the circuitry associated with said wafer with the circuit on the integrated circuit chip, said interconnection being formed by a conductive foil applied by tape automated bonding.